The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high density semiconductor devices with submicron design features and active regions isolated by shallow insulated trenches.
Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by forming field oxide regions by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material such as silicon dioxide derived from tetraethyl orthosilicate (TEOS) to form a field oxide region. The insulating material is then planarized, as by chemical-mechanical polishing (CMP) using the barrier nitride layer as a polish stop, to remove all the oxide over the active regions so that only the trenches are filled. The nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
The planarization of the insulating material is a difficult process, because the field oxide regions vary widely in size. For example, one trench may have a width as little as 0.25 xcexc, while an adjacent trench may be several microns wide. After the insulating material is deposited to fill the trenches and cover the polish stop, fissures called xe2x80x9cseamsxe2x80x9d exist in the deposited insulating material above the smaller trenches, and indentations called xe2x80x9cstepsxe2x80x9d exist in the upper surface of the insulating material above the large trenches. The steps are considerably wider than the seams; however, the seams are considerably deeper than the steps. The presence of both seams and steps is problematic during polishing, in that the greater amount of polishing required to remove the seams over the small features results in the removal of too much insulating material over the large features. This overpolishing of the insulating material above the large trenches produces undesirable xe2x80x9cdishingxe2x80x9d of the insulating material, resulting in a nonplanar insulating surface.
The problem of simultaneously planarizing an insulating material over both large and small features has been addressed by providing preliminary masking and etching steps, and then polishing, as by CMP. This technique is illustrated in FIGS. 1A-1C. Adverting to FIG. 1A, there is schematically illustrated the substrate 11, pad oxide layer 12, polish stop 13, oxide liner 14, trenches 15, insulating layer 16, seams 17 and steps 18. Inverse source/drain photoresist mask 19 is formed on the insulating layer 16 to protect the seams 17 and steps 18 from overetching. Isotropic etching is then performed to remove most of the insulating material in the active areas (FIG. 1B) before the final chemical-mechanical polish, as shown in FIG. 1C.
In principal this works very well. However, as the isotropic etch progresses, the contact area of photoresist mask 19 above small trenches 15 typically narrows down to a point. At this point, photoresist mask 19 detaches from insulating material 16, and the etch process then attacks seams 17. Seams 17 tend to be etched at a faster rate, since they are less compact, causing overetching and undesirable indentation around the seam. Ideally, it would be preferred to etch away all of insulating layer 16 on top of polish stop layer 13, then proceed with CMP to remove the remaining portions of insulating layer 16 (called xe2x80x9cfencesxe2x80x9d) followed by a short polish. However the indentation around seams 17 require a portion of insulating layer 16 be left on top of polish stop layer 13, so the indentation does not extend below the top surface of polish stop layer 13. This remaining portion of insulating layer 16 above polish stop layer 13 contributes to increased non-uniformity of the planarized top surface of insulating 16. Moreover, as minimum device critical dimension (CD) shrinks, indentation of seams 17 happens earlier in the etch process, requiring a higher oxide polish target.
Furthermore, the inverse source/drain mask 19 is a xe2x80x9ccritical maskxe2x80x9d; i.e., it is complex and difficult to design and use. Still further, due to the topography of insulating material layer 16 prior to polishing, a relatively large depth of focus is required to produce mask 19.
Accordingly, there exists a need for a method of manufacturing a shallow trench isolation structure with improved field oxide planarity without the necessity of employing a complex critical mask.
An object of the present invention is a method of manufacturing a semiconductor device having insulated trenches formed in a semiconductor substrate, wherein an insulating material which fills the trenches and acts as the field oxide is planarized using a simplified, non-critical inverse source/drain mask.
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a method of manufacturing a semiconductor device having a plurality of trenches formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises: forming a pad oxide layer on a main surface of the substrate or epitaxial layer; forming a polish stop layer having an upper surface on the pad oxide layer; forming a relatively large trench having side surfaces; depositing a first layer of an insulating material to fill the relatively large trench and cover the polish stop layer, whereby the first layer of the insulating material has a step in its upper surface above the relatively large trench; providing a planarization mask on the first layer of the insulating material above the step; etching to remove substantially all of the first layer of the insulating material on the polish stop layer; removing the planarization mask; performing a first polish to planarize such that an upper surface of the first layer of the insulating material is substantially flush with the upper surface of the polish stop layer; forming a relatively small trench, the relatively small trench having a width at the main surface less than a width at the main surface of the relatively large trench; forming a peripheral trench surrounding the relatively large trench and abutting the side surfaces of the relatively large trench, the peripheral trench having a width at the main surface less than the width at the main surface of the relatively large trench; thermally growing an oxide layer lining the relatively small trench and the peripheral trench; depositing a second layer of the insulating material to fill the relatively small trench and the peripheral trench and cover the polish stop layer; and performing a second polish to planarize such that an upper surface of the second layer of the insulating material is substantially flush with the upper surface of the polish stop layer.
Another aspect of the present invention is a semiconductor device comprising: a substrate or epitaxial layer formed in the substrate; a relatively large trench, formed in a main surface of the substrate or epitaxial layer, having side surfaces; a relatively small trench, formed in the main surface, having a width at the main surface less than a width at the main surface of the relatively large trench; a peripheral trench, formed in the main surface, surrounding the relatively large trench and abutting the side surfaces of the relatively large trench, the peripheral trench having a width at the main surface less than the width at the main surface of the relatively large trench; a thermally grown oxide liner in the relatively small trench and the peripheral trench; and an insulating material filling the relatively large trench, the relatively small trench, and the peripheral trench.
Additional objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.